As the demand for smaller electronic products grows, manufacturers and others in the electronics industry continually seek ways to reduce the size of integrated circuits used in the electronic products. In that regard, three-dimensional (3D) type integrated circuit (IC) packaging techniques have been developed and used.
One packaging technique that has been developed is Package-on-Package (PoP). As the name implies, PoP is a semiconductor packaging innovation that involves stacking one package on top of another package. A PoP device may combine vertically discrete memory and logic packages.
Through package vias (TPVs) are a useful component in the creation of 3D packages and 3D ICs. TPVs permit designers to replace the edge wiring when creating 3D packages (e.g., System in Package, Chip Stack Multi-chip Module).
By using TPVs, designers of 3D packages or 3D ICs are able to reduce the size of the IC or package, e.g. Miniaturization. This is due to the reduced, or eliminated, need for edge wiring as well as the ability to double-side mount both types of active circuits, logic and memory.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.